WOLFRAM SYSTEM MODELER
AbsoluteClocksDrive with clocked cascade controller where all partitions are defined with exact (integer) clock that need to be compatible to each other |
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Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica.Clocked.Examples.CascadeControlledDrive.AbsoluteClocks"]
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Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Cascade control drive with discrete-time controller where two periodic clock with absolute periods are defined and are associated to the corresponding controller partitions. The super-sampling factor of block "super" is derived by clock inference.
Components (16)
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load |
Type: Inertia Description: 1D-rotational component with inertia |
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speed |
Type: SpeedSensor Description: Ideal sensor to measure the absolute flange angular velocity |
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PI |
Type: PI Description: Discrete-time PI controller with clocked input and output signals (for periodic and aperiodic systems using the parameterization of the continuous PI controller) |
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feedback2 |
Type: Feedback Description: Output difference between commanded and feedback input |
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torque |
Type: Torque Description: Input signal acting as external torque on a flange |
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angle |
Type: AngleSensor Description: Ideal sensor to measure the absolute flange angle |
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kinematicPTP |
Type: KinematicPTP2 Description: Move as fast as possible from start to end position within given kinematic constraints with output signals q, qd=der(q), qdd=der(qd) |
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feedback1 |
Type: Feedback Description: Output difference between commanded and feedback input |
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gain |
Type: Gain Description: Output the product of a gain value with the input signal |
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sample1 |
Type: SampleClocked Description: Sample the continuous-time, Real input signal and provide it as clocked output signal. The clock is provided as input signal |
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sample2 |
Type: Sample Description: Sample the continuous-time, Real input signal and provide it as clocked output signal (clock is inferred) |
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hold1 |
Type: Hold Description: Hold the clocked, Real input signal and provide it as continuous-time output signal (zero order hold) |
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sample3 |
Type: SampleClocked Description: Sample the continuous-time, Real input signal and provide it as clocked output signal. The clock is provided as input signal |
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super |
Type: SuperSample Description: Super-sample the clocked Real input signal and provide it as clocked output signal |
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slowClock |
Type: PeriodicExactClock Description: Generate a periodic clock signal with a period defined by an Integer number with resolution |
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fastClock |
Type: PeriodicExactClock Description: Generate a periodic clock signal with a period defined by an Integer number with resolution |