WOLFRAM SYSTEM MODELER
SampleVectorizedAndClockedExample of a SampleVectorizedAndClocked block for Real signals |
 |
Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica.Clocked.Examples.Elementary.RealSignals.SampleVectorizedAndClocked"]
Out[1]:=
Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Example used to generate a figure for the documentation of block Modelica.Clocked.RealSignals.Sampler.SampleVectorizedAndClocked.
Components (4)
 |
sine2 |
Type: Sine Description: Generate sine signal |
|---|---|---|
 |
sample1 |
Type: SampleVectorizedAndClocked Description: Sample the continuous-time, Real input signal vector and provide it as clocked output signal vector. The clock is provided as input signal |
 |
periodicClock |
Type: PeriodicExactClock Description: Generate a periodic clock signal with a period defined by an Integer number with resolution |
|
sine1 |
Type: Sine Description: Generate sine signal |