WOLFRAM SYSTEM MODELER
RAMSimple RAM test example |
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Diagram
Wolfram Language
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SystemModel["Modelica.Electrical.Digital.Examples.RAM"]
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Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
This example is a simple and uncomplete test of a single DLATRAM component . After simulation until 400 s plot dLATRAM.addr[1], dLATRAM.addr[2], and dLATRAM.dataOUT[1], dLATRAM.dataOut[2]. The address inputs are prescribed with all possible combinations of logic values. It can be checked in which cases of address values the output is 'X' or '0'.
Components (7)
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dLATRAM |
Type: DLATRAM Description: Level sensitive Random Access Memory |
|---|---|---|
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addr_1 |
Type: Table Description: Digital Tabular Source |
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data_1 |
Type: Set Description: Digital Set Source |
|
data_0 |
Type: Set Description: Digital Set Source |
|
WE |
Type: Set Description: Digital Set Source |
|
addr_0 |
Type: Table Description: Digital Tabular Source |
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RE |
Type: Set Description: Digital Set Source |