WOLFRAM

WOLFRAM SYSTEM MODELER

Table

Digital Tabular Source

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Sources.Table"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

The table source output signal y steps to the values of the x table at the corresponding timepoints in the t table.
The initial value is specified by y0.

To specify the logic value parameters, the integer code has to be used.

Code Table

Logic value Integer code Meaning
'U' 1 Uninitialized
'X' 2 Forcing Unknown
'0' 3 Forcing 0
'1' 4 Forcing 1
'Z' 5 High Impedance
'W' 6 Weak Unknown
'L' 7 Weak 0
'H' 8 Weak 1
'-' 9 Do not care

If the logic values are imported by
import L = Digital.Interfaces.Logic;
they can be used to specify the parameter, e.g., L.'0' for forcing 0.

Parameters (4)

x

Value: {L.'1'}

Type: Logic[:]

Description: Vector of values
t

Value: {1}

Type: Real[size(x, 1)]

Description: Vector of corresponding time points
y0

Value: L.'U'

Type: Logic

Description: Initial output value
n

Value: size(x, 1)

Type: Integer

Description: Table size

Connectors (1)

y

Type: DigitalOutput

Description: Output DigitalSignal as connector

Used in Examples (20)

Multiplexer

Modelica.Electrical.Digital.Examples

4 to 1 Bit Multiplexer Example

FlipFlop

Modelica.Electrical.Digital.Examples

Pulse Triggered Master Slave Flip-Flop

HalfAdder

Modelica.Electrical.Digital.Examples

Adding circuit for binary numbers without input carry bit

Adder4

Modelica.Electrical.Digital.Examples

4 Bit Adder Example

VectorDelay

Modelica.Electrical.Digital.Examples

Vector delay

DFFREG

Modelica.Electrical.Digital.Examples

Pulse triggered D-Register-Bank, high active reset

DFFREGL

Modelica.Electrical.Digital.Examples

Pulse triggered D-Register-Bank, low active reset

DFFREGSRH

Modelica.Electrical.Digital.Examples

Pulse triggered D-Register-Bank, high active set and reset

DFFREGSRL

Modelica.Electrical.Digital.Examples

Pulse triggered D-Register-Bank, low active set and reset

DLATREG

Modelica.Electrical.Digital.Examples

Level sensitive D-Register-Bank, high active reset

DLATREGL

Modelica.Electrical.Digital.Examples

Level sensitive D-Register-Bank, low active reset

DLATREGSRH

Modelica.Electrical.Digital.Examples

Level sensitive D-Register-Bank, high active set and reset

DLATREGSRL

Modelica.Electrical.Digital.Examples

Level sensitive D-Register-Bank, low active set and reset

NXFER

Modelica.Electrical.Digital.Examples

Functionality test of NXFERGATE

NRXFER

Modelica.Electrical.Digital.Examples

Functionality test of NRXFERGATE

BUF3S

Modelica.Electrical.Digital.Examples

Functionality test of BUF3S

INV3S

Modelica.Electrical.Digital.Examples

Functionality test of INV3S

WiredX

Modelica.Electrical.Digital.Examples

Functionality test of WiredX

MUX2x1

Modelica.Electrical.Digital.Examples

Simple Multiplexer test

RAM

Modelica.Electrical.Digital.Examples

Simple RAM test example

Revisions

August 20, 2003
by Teresa Schlegel initially modelled.