WOLFRAM SYSTEM MODELER
DFFREGSRLPulse triggered D-Register-Bank, low active set and reset |
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Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica.Electrical.Digital.Examples.DFFREGSRL"]
Out[1]:=
Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
This example is a simple test of the Registers.DFFREGSRL component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DFFREGSRL component.
Components (6)
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clock |
Type: Table Description: Digital Tabular Source |
|---|---|---|
|
data_0 |
Type: Table Description: Digital Tabular Source |
|
reset |
Type: Table Description: Digital Tabular Source |
|
data_1 |
Type: Table Description: Digital Tabular Source |
|
set |
Type: Table Description: Digital Tabular Source |
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dFFREGSRL |
Type: DFFREGSRL Description: Edge triggered register bank with low active set and reset |