WOLFRAM SYSTEM MODELER

DFFREGSRL

Edge triggered register bank with low active set and reset

Diagram

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Registers.DFFREGSRL"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn Clock Reset Set DataOut
* * * U U
* * U * U
* * * 0 1
* * 0 1 0
* * 0 X X
* * X X X or U
* * 1 X X or U or 1 or NC
* * X 1 X or U or 0 or NC
* X-Trns 1 1 X or U or NC
* 1-Trns 1 1 DataIn
* 0-Trns 1 1 NC
  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters (4)

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

strength

Value: S.'S_X01'

Type: Strength

Description: Output strength

n

Value: 1

Type: Integer

Description: Data width

Connectors (5)

set

Type: DigitalInput

Description: Input DigitalSignal as connector

reset

Type: DigitalInput

Description: Input DigitalSignal as connector

clock

Type: DigitalInput

Description: Input DigitalSignal as connector

dataIn

Type: DigitalInput[n]

Description: Input DigitalSignal as connector

dataOut

Type: DigitalOutput[n]

Description: Output DigitalSignal as connector

Components (2)

delay

Type: InertialDelaySensitiveVector

Description: Delay of a vector of digital signals

dFFSR

Type: DFFSR

Description: Edge triggered register bank with set and reset

Used in Examples (1)

DFFREGSRL

Modelica.Electrical.Digital.Examples

Pulse triggered D-Register-Bank, low active set and reset

Revisions

  • September 11, 2009 created by Ulrich Donath