WOLFRAM SYSTEMMODELER

FlipFlop

Pulse Triggered Master Slave Flip-Flop

Diagram

Wolfram Language

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SystemModel["Modelica.Electrical.Digital.Examples.FlipFlop"]
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Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

A pulse-triggered master-slave flip-flop is demonstrated. The flipflop component is composed by basic gates. It can be found in the Utilities subpackage. The example is designed to test and demonstrate the basic gate components.

Components (4)

FF

Type: JKFF

CLK

Type: Clock

J

Type: Table

K

Type: Table