WOLFRAM SYSTEM MODELER

SampleVectorizedAndClocked

Example of a SampleVectorizedAndClocked block for Real signals

Diagram

Wolfram Language

In[1]:=
SystemModel["Modelica_Synchronous.Examples.Elementary.RealSignals.SampleVectorizedAndClocked"]
Out[1]:=

Information

Example used to generate a figure for the documentation of block Modelica_Synchronous.RealSignals.Sampler.SampleVectorizedAndClocked.

Components (4)

sine2

Type: Sine

Description: Generate sine signal

sample

Type: SampleVectorizedAndClocked

Description: Sample the continuous-time, Real input signal vector and provide it as clocked output signal vector. The clock is provided as input signal

periodicClock

Type: PeriodicExactClock

Description: Generates a periodic clock signal with a period defined by an Integer number with resolution

sine1

Type: Sine

Description: Generate sine signal