WOLFRAM SYSTEM MODELER
SampleVectorizedAndClockedExample of a SampleVectorizedAndClocked block for Real signals |
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Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica_Synchronous.Examples.Elementary.RealSignals.SampleVectorizedAndClocked"]
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Information
Example used to generate a figure for the documentation of block Modelica_Synchronous.RealSignals.Sampler.SampleVectorizedAndClocked.
Components (4)
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sine2 |
Type: Sine Description: Generate sine signal |
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sample |
Type: SampleVectorizedAndClocked Description: Sample the continuous-time, Real input signal vector and provide it as clocked output signal vector. The clock is provided as input signal |
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periodicClock |
Type: PeriodicExactClock Description: Generates a periodic clock signal with a period defined by an Integer number with resolution |
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sine1 |
Type: Sine Description: Generate sine signal |