WOLFRAM SYSTEM MODELER
TestBackSample |
Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica_Synchronous.WorkInProgress.Tests.TestBackSample"]
Out[1]:=
Components (7)
 |
sine |
Type: Sine Description: Generate sine signal |
|---|---|---|
 |
periodicRealClock |
Type: PeriodicRealClock Description: Generates a periodic clock signal with a period defined by a Real number |
 |
sample1 |
Type: SampleClocked Description: Sample the continuous-time, Real input signal and provide it as clocked output signal. The clock is provided as input signal |
 |
shiftSample1 |
Type: ShiftSample Description: Shift the clocked Real input signal by a fraction of the last interval and and provide it as clocked output signal |
 |
backSample2 |
Type: BackSample Description: Shift the clock of the Real input signal backwards in time (and access the most recent value of the input at this new clock) |
 |
add |
Type: Add Description: Output the sum of the two inputs |
|
backSample3 |
Type: BackSample Description: Shift the clock of the Real input signal backwards in time (and access the most recent value of the input at this new clock) |