WOLFRAM SYSTEM MODELER

TestEventClockWithIntegrator

Diagram

Wolfram Language

In[1]:=
SystemModel["Modelica_Synchronous.WorkInProgress.Tests.TestEventClockWithIntegrator"]
Out[1]:=

Components (5)

eventClock

Type: EventClock

Description: Generates a clock signal when the Boolean input changes from false to true

booleanPulse

Type: BooleanPulse

Description: Generate pulse signal of type Boolean

firstOrder

Type: FirstOrder

Description: First order transfer function block (= 1 pole)

sine

Type: Sine

Description: Generate sine signal

sample1

Type: SampleClocked

Description: Sample the continuous-time, Real input signal and provide it as clocked output signal. The clock is provided as input signal