This information is part of the Modelica Standard Library maintained by the Modelica Association.

The nand gate is a basic CMOS building block. It consists of four CMOS transistors. The output voltage Nand.y.v is low if and only if the two input voltages at Nand.x1.v and Nand.x2.v are both high. In this way the nand functionality is realized.

The simulation end time should be set to 1e-7. Please plot the input voltages Nand.x1.v, d Nand.x2.v, and the output voltage Nand.y.v.

Reference:

Tietze, U.; Schenk, Ch.: Halbleiter-Schaltungstechnik. Springer-Verlag Berlin Heidelberg NewYork 1980, p. 157

Main Authors:

Christoph Clauß <christoph@clauss-it.com>
André Schneider <Andre.Schneider@eas.iis.fraunhofer.de>
Fraunhofer Institute for Integrated Circuits
Design Automation Department
Zeunerstraße 38
D-01069 Dresden