WOLFRAM SYSTEMMODELER

NRXFERGATE

Transfergate with enable active high. Output strength reduced.

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Tristates.NRXFERGATE"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn Enable DataOut
* U U
* X UW
* 0 Z
* 1 DataIn, Strength Reduced
* Z UW
* W UW
* L Z
* H DataIn, Strength Reduced
* - UW
  UW: if dataIn == U then U else W
  Strength Reduced: 0 -> L, 1 -> H, X -> W

Parameters (2)

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

Connectors (3)

enable

Type: DigitalInput

x

Type: DigitalInput

y

Type: DigitalOutput

Components (1)

inertialDelaySensitive

Type: InertialDelaySensitive

Used in Examples (1)

NRXFER

Modelica.Electrical.Digital.Examples

Functionality test of NRXFERGATE