WOLFRAM SYSTEM MODELER
PRXFERGATETransfergate with enable active low. Output strength reduced. |
 |
Wolfram Language
In[1]:=
SystemModel["Modelica.Electrical.Digital.Tristates.PRXFERGATE"]
Out[1]:=
Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Enable | DataOut |
| * | U | U |
| * | X | UW |
| * | 0 | DataIn, Strength Reduced |
| * | 1 | Z |
| * | Z | UW |
| * | W | UW |
| * | L | DataIn, Strength Reduced |
| * | H | Z |
| * | - | UW |
UW: if dataIn == U then U else W Strength Reduced: 0 -> L, 1 -> H, X -> W
Parameters (2)
Connectors (4)
 |
enable |
Type: DigitalInput Description: Input DigitalSignal as connector |
|---|---|---|
|
x |
Type: DigitalInput Description: Input DigitalSignal as connector |
 |
y |
Type: DigitalOutput Description: Output DigitalSignal as connector |
|
yy |
Type: DigitalOutput Description: Output DigitalSignal as connector |
Components (1)
 |
inertialDelaySensitive |
Type: InertialDelaySensitive Description: Provide the input as output if it holds its value for a specific amount of time |
|---|
Revisions
- January 15, 2010 created by Ulrich Donath