WOLFRAM SYSTEM MODELER
UnitDelayDelays the clocked input signal for one sample period |
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Wolfram Language
In[1]:=
SystemModel["Modelica_Synchronous.IntegerSignals.NonPeriodic.UnitDelay"]
Out[1]:=
Information
This block describes a unit delay:
// Time domain description
y(ti) = previous(u(ti))
// Discrete transfer function
1
y(z) = --- * u(z)
z
that is, the output signal y is the input signal u at the previous clock tick. At the first clock tick, the output y is set to parameter y_start.
Parameters (1)
| y_start |
Value: 0 Type: Integer Description: Value of output signal at first clock tick |
|---|
Connectors (2)
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u |
Type: IntegerInput Description: Connector of clocked, Real input signal |
|---|---|---|
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y |
Type: IntegerOutput Description: Connector of clocked, Real output signal |
Used in Examples (3)
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Modelica_Synchronous.Examples.Elementary.IntegerSignals Example of an AssignClock block for Integer signals |
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Modelica_Synchronous.Examples.Elementary.IntegerSignals Example of an AssignClockVectorized block for Integer signals |
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Modelica_Synchronous.WorkInProgress.Tests |