WOLFRAM SYSTEM MODELER

UnitDelay

Delays the clocked input signal for one sample period

Wolfram Language

In[1]:=
SystemModel["Modelica_Synchronous.RealSignals.NonPeriodic.UnitDelay"]
Out[1]:=

Information

This block describes a unit delay: 

  // Time domain description
     y(ti) = previous(u(ti))

  // Discrete transfer function
             1
     y(z) = --- * u(z)
             z

that is, the output signal y is the input signal u at the previous clock tick. At the first clock tick, the output y is set to parameter y_start.

Parameters (1)

y_start

Value: 0

Type: Real

Description: Value of output signal at first clock tick

Connectors (2)

u

Type: RealInput

Description: Connector of clocked, Real input signal
y

Type: RealOutput

Description: Connector of clocked, Real output signal

Used in Examples (3)

AssignClock

Modelica_Synchronous.Examples.Elementary.RealSignals

Example of a AssignClock block for Real signals

AssignClockVectorized

Modelica_Synchronous.Examples.Elementary.RealSignals

Example of a AssignClockVectorized block for Real signals

TestUnitDelay

Modelica_Synchronous.WorkInProgress.Tests