WOLFRAM SYSTEM MODELER
TestUnitDelay |
Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica_Synchronous.WorkInProgress.Tests.TestUnitDelay"]
Out[1]:=
Components (4)
 |
sine |
Type: Sine Description: Generate sine signal |
|---|---|---|
 |
sample1 |
Type: SampleClocked Description: Sample the continuous-time, Real input signal and provide it as clocked output signal. The clock is provided as input signal |
 |
periodicRealClock |
Type: PeriodicRealClock Description: Generates a periodic clock signal with a period defined by a Real number |
 |
UnitDelay1 |
Type: UnitDelay Description: Delays the clocked input signal for one sample period |