WOLFRAM SYSTEM MODELER

Not

Not logic component without delay

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Basic.Not"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Not component with 1 input value, without delay.

According to the standard logic not table (Tables.NotTable) the output value is calculated.

To avoid loops in the numerical treatment, the pre operator is applied to the output.

Connectors (2)

x

Type: DigitalInput

Description: Connector of Digital input signal
y

Type: DigitalOutput

Description: Connector of Digital output signal

Used in Components (4)

MUX4

Modelica.Electrical.Digital.Examples.Utilities

4 to 1 Bit Multiplexer

DFF

Modelica.Electrical.Digital.Examples.Utilities

D FlipFlop

JKFF

Modelica.Electrical.Digital.Examples.Utilities

JK FlipFlop

InvGate

Modelica.Electrical.Digital.Gates

InvGate with 1 input value, composed by Not and sensitive inertial delay

Revisions

August 14, 2003
by Teresa Schlegel initially modelled.