WOLFRAM SYSTEM MODELER
NotNot logic component without delay |
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Wolfram Language
In[1]:=
SystemModel["Modelica.Electrical.Digital.Basic.Not"]
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Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Not component with 1 input value, without delay.
According to the standard logic not table (Tables.NotTable) the output value is calculated.
To avoid loops in the numerical treatment, the pre operator is applied to the output.
Connectors (2)
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x |
Type: DigitalInput Description: Connector of Digital input signal |
|---|---|---|
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y |
Type: DigitalOutput Description: Connector of Digital output signal |
Used in Components (4)
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Modelica.Electrical.Digital.Examples.Utilities 4 to 1 Bit Multiplexer |
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Modelica.Electrical.Digital.Examples.Utilities D FlipFlop |
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Modelica.Electrical.Digital.Examples.Utilities JK FlipFlop |
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Modelica.Electrical.Digital.Gates InvGate with 1 input value, composed by Not and sensitive inertial delay |
Revisions
- August 14, 2003
- by Teresa Schlegel initially modelled.