WOLFRAM SYSTEM MODELER
DLATROMLevel sensitive Read Only Memory |
 |
Wolfram Language
In[1]:=
SystemModel["Modelica.Electrical.Digital.Memories.DLATROM"]
Out[1]:=
Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active read enable RE:
| RE | Addr | DataOut |
| 0 | * | Z over all |
| 1 | no X in Addr | DataOut=m(Addr) |
| 1 | X in Addr | X over all |
| X | * | X over all |
* = do not care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U' Z = L.'Z'
Parameters (6)
| tHL |
Value: 0 Type: Time (s) Description: High->Low delay |
|---|---|
| tLH |
Value: 0 Type: Time (s) Description: Low->High delay |
| strength |
Value: S.'S_X01' Type: Strength Description: Output strength |
| n_addr |
Value: 2 Type: Integer Description: Addr width |
| n_data |
Value: 2 Type: Integer Description: Data width |
| fileName |
Value: Modelica.Utilities.Files.loadResource("modelica://Modelica/Resources/Data/Electrical/Digital/Memory_Matrix.txt") Type: String Description: File where matrix for memory is stored |
Connectors (4)
 |
RE |
Type: DigitalInput Description: Read enable |
|---|---|---|
|
addr |
Type: DigitalInput[n_addr] Description: Address |
 |
dataOut |
Type: DigitalOutput[n_data] Description: Data output |
|
yy |
Type: DigitalOutput[n_data] Description: Output DigitalSignal as connector |
Components (1)
 |
inertialDelaySensitive |
Type: InertialDelaySensitive[n_data] Description: Provide the input as output if it holds its value for a specific amount of time |
|---|
Revisions
- October 19, 2010
- created by Ulrich Donath