WOLFRAM SYSTEMMODELER

BUF3SL

Tristate buffer with enable active low

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Tristates.BUF3SL"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

DataIn Enable DataOut*
* U U
* X UX
* 0 DataIn
* 1 Z
* Z UX
* W UX
* L DataIn
* H Z
* - UX
  UX: if dataIn == U then U else X
  DataOut*: Strength map for DataOut according to tristate table Buf3slTable

Parameters (3)

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

strength

Value: S.'S_X01'

Type: Strength

Description: output strength

Connectors (3)

enable

Type: DigitalInput

x

Type: DigitalInput

y

Type: DigitalOutput

Components (1)

inertialDelaySensitive

Type: InertialDelaySensitive