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WOLFRAM SYSTEM MODELER

INV3SL

Tristate inverter with enable active low

Wolfram Language

In[1]:=

SystemModel["Modelica.Electrical.Digital.Tristates.INV3SL"]

Out[1]:=

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

UX: if dataIn == U then U else X
DataOut*: Strength map for DataOut according to tristate table Buf3slTable

tHL	Value: 0 Type: Time (s) Description: High->Low delay
tLH	Value: 0 Type: Time (s) Description: Low->High delay
strength	Value: S.'S_X01' Type: Strength Description: Output strength

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

strength

Value: S.'S_X01'

Description: Output strength

	enable	Type: DigitalInput Description: Input DigitalSignal as connector
	x	Type: DigitalInput Description: Input DigitalSignal as connector
	y	Type: DigitalOutput Description: Output DigitalSignal as connector
	yy	Type: DigitalOutput Description: Output DigitalSignal as connector

	inertialDelaySensitive	Type: InertialDelaySensitive Description: Provide the input as output if it holds its value for a specific amount of time

inertialDelaySensitive

Description: Provide the input as output if it holds its value for a specific amount of time