WOLFRAM SYSTEM MODELER
TestSimulatedADC |
Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica_Synchronous.WorkInProgress.Tests.TestSimulatedADC"]
Out[1]:=
Components (7)
 |
sine |
Type: Sine Description: Generate sine signal |
|---|---|---|
 |
periodicRealClock |
Type: PeriodicRealClock Description: Generates a periodic clock signal with a period defined by a Real number |
 |
sample1 |
Type: SampleWithADeffects Description: Sample with (simulated) Analog-Digital converter effects including noise |
 |
assignClock1 |
Type: AssignClock Description: Assigns a clock to a clocked Real signal |
 |
hold1 |
Type: HoldWithDAeffects Description: Hold with (simulated) Digital-Analog converter effects and computational delay |
|
sample2 |
Type: SampleWithADeffects Description: Sample with (simulated) Analog-Digital converter effects including noise |
|
assignClock2 |
Type: AssignClock Description: Assigns a clock to a clocked Real signal |