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WOLFRAM SYSTEM MODELER

AssignClock

Assigns a clock to a clocked Real signal

Wolfram Language

In[1]:=

SystemModel["Modelica_Synchronous.RealSignals.Sampler.AssignClock"]

Out[1]:=

Information

This block assigns a clock to the Real input signal u and provides u as output signal y.

Example

The following example shows a discrete counter. In order to execute the counter with a sample period of 20ms an AssignClock block is used. Due to clock inference all equations within the blocks are deduced to be active at the clock ticks given by the periodicClock block.


	model	simulation result

At every clock tick (that is at every 20ms) the output of the unitDelay1 block is incremented by one.

Connectors (3)

	u	Type: RealInput Description: Connector of clocked, Real input signal
	y	Type: RealOutput Description: Connector of clocked, Real output signal
	clock	Type: ClockInput Description: 'input Clock' as connector

Type: RealInput

Description: Connector of clocked, Real input signal

Type: RealOutput

Description: Connector of clocked, Real output signal

clock

Type: ClockInput

Description: 'input Clock' as connector

Used in Examples (9)

	ClockedWith_AD_DA_Effects Modelica_Synchronous.Examples.SimpleControlledDrive Simple controlled drive with discrete controller and simulated AD and DA effects
	Sample1 Modelica_Synchronous.Examples.Elementary.RealSignals Example of a Sample block for Real signals
	Sample2 Modelica_Synchronous.Examples.Elementary.RealSignals Example of a Sample block with discontinuous Real input signals
	SampleWithADeffects Modelica_Synchronous.Examples.Elementary.RealSignals Example of a SampleWithADeffects block for Real signals
	AssignClock Modelica_Synchronous.Examples.Elementary.RealSignals Example of a AssignClock block for Real signals
	TestInterpolator Modelica_Synchronous.WorkInProgress.Tests
	TestReplaceableSamplerHold Modelica_Synchronous.WorkInProgress.Tests Using partial sample and hold blocks to allow redeclaration of blocks to simulated communication blocks
	TestSimulatedADC Modelica_Synchronous.WorkInProgress.Tests
	TestCommunicationDelay Modelica_Synchronous.WorkInProgress.Tests

Used in Components (6)

	TimeBasedStep Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked simulation time based Step source block
	TickBasedStep Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked tick based Step source block
	TimeBasedSine Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked time based Sine source block
	TickBasedSine Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked tick based Sine source block
	TimeBasedRamp Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked time based Ramp source block
	TickBasedRamp Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked tick based Ramp source block

Revisions

Date	Author	Company/Institute	Comment
2012-08-20	Bernhard Thiele	DLR, Institute for System Dynamics and Control	Initial version