WOLFRAM SYSTEM MODELER
AssignClockAssigns a clock to a clocked Real signal |
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Wolfram Language
In[1]:=
SystemModel["Modelica_Synchronous.RealSignals.Sampler.AssignClock"]
Out[1]:=
Information
This block assigns a clock to the Real input signal u and provides u as output signal y.
Example
The following
example
shows a discrete counter. In order to execute the counter with a sample period of 20ms an AssignClock block is used. Due to clock inference all equations within the blocks are deduced to be active at the clock ticks given by the periodicClock block.
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| model | simulation result |
At every clock tick (that is at every 20ms) the output of the unitDelay1 block is incremented by one.
Connectors (3)
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u |
Type: RealInput Description: Connector of clocked, Real input signal |
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y |
Type: RealOutput Description: Connector of clocked, Real output signal |
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clock |
Type: ClockInput Description: 'input Clock' as connector |
Used in Examples (9)
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Modelica_Synchronous.Examples.SimpleControlledDrive Simple controlled drive with discrete controller and simulated AD and DA effects |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of a Sample block for Real signals |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of a Sample block with discontinuous Real input signals |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of a SampleWithADeffects block for Real signals |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of a AssignClock block for Real signals |
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Modelica_Synchronous.WorkInProgress.Tests |
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Modelica_Synchronous.WorkInProgress.Tests Using partial sample and hold blocks to allow redeclaration of blocks to simulated communication blocks |
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Modelica_Synchronous.WorkInProgress.Tests |
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Modelica_Synchronous.WorkInProgress.Tests |
Used in Components (6)
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked simulation time based Step source block |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked tick based Step source block |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked time based Sine source block |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked tick based Sine source block |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked time based Ramp source block |
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Modelica_Synchronous.Examples.Elementary.RealSignals Example of using the clocked tick based Ramp source block |
Revisions
| Date | Author | Company/Institute | Comment |
|---|---|---|---|
| 2012-08-20 | Bernhard Thiele | DLR, Institute for System Dynamics and Control | Initial version |