WOLFRAM SYSTEM MODELER
DisjunctiveClockLogical clock ticking whenever any of its input clock signals ticks. |
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Diagram
Wolfram Language
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SystemModel["Modelica.Clocked.ClockSignals.Clocks.Logical.DisjunctiveClock"]
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Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
For a simple example cf. the logical sampling example.Parameters (3)
| useSolver |
Value: false Type: Boolean Description: = true, if solverMethod shall be explicitly defined |
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| solverMethod |
Value: "ExplicitEuler" Type: SolverMethod Description: Integration method used for discretized continuous-time partitions |
| nu |
Value: 2 Type: Integer Description: Number of input connections. |
Connectors (2)
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y |
Type: ClockOutput Description: 'output Clock' as connector |
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u |
Type: ClockVectorInput[nu] Description: Vector of Clock input signals. |
Components (9)
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combinator |
Type: Or Description: Replaceable logical combinator applied on vector of Clock input signals. Important: Must not be any kind of negation since such would result in infinite many ticks for an infinitesimal short time period. |
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clock |
Type: EventClock Description: Generate a clock signal when the Boolean input changes from false to true |
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input_ticked |
Type: ClockToBoolean[nu] Description: Block to translate clock signals to continuous Boolean events (each time the input clock ticks a rising Boolean output edge is produced). |
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forbidden_state |
Type: And[nu] Description: Logical 'and': y = u1 and u2 |
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S_false |
Type: BooleanConstant[nu] Description: Generate constant signal of type Boolean |
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suppress_S |
Type: LogicalSwitch[nu] Description: Logical Switch |
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input_memory |
Type: RSFlipFlop[nu] Description: A basic RS Flip Flop |
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reset_ticked |
Type: ClockToBoolean Description: Block to translate clock signals to continuous Boolean events (each time the input clock ticks a rising Boolean output edge is produced). |
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splitter |
Type: BooleanReplicator Description: Boolean signal replicator |
Used in Examples (1)
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Modelica.Clocked.Examples.Elementary.ClockSignals Simple example of conjunctive and disjunctive logical clocks, combining clock signals to derive new event driven clocks. |