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WOLFRAM SYSTEM MODELER

RS

Unclocked RS FlipFlop

Diagram

Wolfram Language

In[1]:=

SystemModel["Modelica.Electrical.Digital.Examples.Utilities.RS"]

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Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

RS is a basic component for e.g., the RS (set-reset) flipflop, which is built up by Nor gates according to the schematic. To avoid a numerical loop a small transport delay is inserted which delay time is a parameter of the RS component. Also its initial value can be set by parameter.

Parameters (2)

delayTime	Value: 0 Type: Time (s) Description: Delay time
q0	Value: L.'U' Type: Logic Description: Initial value of output

delayTime

Value: 0

Type: Time (s)

Description: Delay time

Value: L.'U'

Type: Logic

Description: Initial value of output

Connectors (4)

	s	Type: DigitalInput Description: Input DigitalSignal as connector
	r	Type: DigitalInput Description: Input DigitalSignal as connector
	q	Type: DigitalOutput Description: Output DigitalSignal as connector
	qn	Type: DigitalOutput Description: Output DigitalSignal as connector

Components (3)

	Nor1	Type: Nor Description: Nor logic component with multiple input and one output
	Nor2	Type: Nor Description: Nor logic component with multiple input and one output
	TD1	Type: TransportDelay Description: Transport delay with initial parameter