WOLFRAM SYSTEMMODELER

DLATR

Level sensitive register bank with reset

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Registers.DLATR"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active reset:

DataIn Enable Reset DataOut Map
* * U U 1
* * 1 0 2
* 0 0 NC 3
* 1 0 DataIn 3
* X 0 X or U or NC 3
* U ~1 U 4
* ~U X X or U or 0 or NC 4

Truth Table for low active reset:

DataIn Enable Reset DataOut Map
* * U U 1
* * 0 0 2
* 0 1 NC 3
* 1 1 DataIn 3
* X 1 X or U or NC 3
* U ~0 U 4
* ~U X X or U or 0 or NC 4

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Parameters (3)

ResetMap

Value: {1, 4, 3, 2, 4, 4, 3, 2, 4}

Type: Integer[L]

Description: function selection, defaults for high active reset

strength

Value: S.'S_X01'

Type: Strength

Description: output strength

n

Value: 1

Type: Integer

Description: data width

Connectors (4)

reset

Type: DigitalInput

enable

Type: DigitalInput

dataIn

Type: DigitalInput[n]

dataOut

Type: DigitalOutput[n]

Used in Components (1)

DLATREG

Modelica.Electrical.Digital.Registers

Level sensitive register bank with reset active high