WOLFRAM SYSTEMMODELER

DLATREG

Level sensitive register bank with reset active high

Diagram

Wolfram Language

In[1]:=
SystemModel["Modelica.Electrical.Digital.Registers.DLATREG"]
Out[1]:=

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn Enable Reset DataOut
* * U U
* * 1 0
* 0 0 NC
* 1 0 DataIn
* X 0 X or U or NC
* U ~1 U
* ~U X X or U or 0 or NC
  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Parameters (4)

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

strength

Value: S.'S_X01'

Type: Strength

Description: output strength

n

Value: 1

Type: Integer

Description: data width

Connectors (4)

reset

Type: DigitalInput

enable

Type: DigitalInput

dataIn

Type: DigitalInput[n]

dataOut

Type: DigitalOutput[n]

Components (2)

delay

Type: InertialDelaySensitiveVector

dLATR

Type: DLATR

Used in Examples (1)

DLATREG

Modelica.Electrical.Digital.Examples

Level sensitive D-Register-Bank, high active reset

Extended by (1)

DLATREGL

Modelica.Electrical.Digital.Registers

Level sensitive register bank with reset active low