WOLFRAM SYSTEM MODELER
DLATREGLLevel sensitive register bank with reset active low |
SystemModel["Modelica.Electrical.Digital.Registers.DLATREGL"]
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
DataIn | Enable | Reset | DataOut |
* | * | U | U |
* | * | 0 | 0 |
* | 0 | 1 | NC |
* | 1 | 1 | DataIn |
* | X | 1 | X or U or NC |
* | U | ~0 | U |
* | ~U | X | X or U or 0 or NC |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change
reset |
Type: DigitalInput Description: Input DigitalSignal as connector |
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---|---|---|
enable |
Type: DigitalInput Description: Input DigitalSignal as connector |
|
dataIn |
Type: DigitalInput[n] Description: Input DigitalSignal as connector |
|
dataOut |
Type: DigitalOutput[n] Description: Output DigitalSignal as connector |
delay |
Type: InertialDelaySensitiveVector Description: Delay of a vector of digital signals |
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dLATR |
Type: DLATR Description: Level sensitive register bank with reset |
Modelica.Electrical.Digital.Examples Level sensitive D-Register-Bank, low active reset |