WOLFRAM SYSTEM MODELER
DLATREGLLevel sensitive register bank with reset active low |
 |
Diagram
Wolfram Language
In[1]:=
SystemModel["Modelica.Electrical.Digital.Registers.DLATREGL"]
Out[1]:=
Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Enable | Reset | DataOut |
| * | * | U | U |
| * | * | 0 | 0 |
| * | 0 | 1 | NC |
| * | 1 | 1 | DataIn |
| * | X | 1 | X or U or NC |
| * | U | ~0 | U |
| * | ~U | X | X or U or 0 or NC |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change
Parameters (4)
Connectors (4)
 |
reset |
Type: DigitalInput |
|---|---|---|
|
enable |
Type: DigitalInput |
|
dataIn |
Type: DigitalInput[n] |
 |
dataOut |
Type: DigitalOutput[n] |
Components (2)
 |
delay | |
|---|---|---|
 |
dLATR |
Type: DLATR |
Used in Examples (1)
 |
Modelica.Electrical.Digital.Examples Level sensitive D-Register-Bank, low active reset |
Revisions
- September 11, 2009 created by Ulrich Donath