WOLFRAM SYSTEM MODELER

PI

Discrete-time PI controller with clocked input and output signals (for periodic and aperiodic systems using the parameterization of the continuous PI controller)

Wolfram Language

In[1]:=
SystemModel["Modelica_Synchronous.RealSignals.NonPeriodic.PI"]
Out[1]:=

Information

Discrete-time PI controller that has been derived from the continuous-time PI controller 

                 1
   y = k * (1 + ---) * u
                T*s
           T*s + 1
     = k * ------- * u
             T*s

by using the implicit Euler discretization formula. The block is parametrized with the gain k and the time constant T of the continuous PI block. As a result, the discrete-time form of the PI controller depends explicitly on the sample time of the controller and changing this sample time, will give still a similar performance.

Parameters (2)

k

Value:

Type: Real

Description: Gain of continuous PI controller
T

Value:

Type: Real

Description: Time constant of continuous PI controller

Outputs (1)

x

Type: Real

Description: Discrete PI state

Connectors (2)

u

Type: RealInput

Description: Connector of clocked, Real input signal
y

Type: RealOutput

Description: Connector of clocked, Real output signal

Used in Examples (7)

ClockedWithDiscreteController

Modelica_Synchronous.Examples.SimpleControlledDrive

Simple controlled drive with discrete controller (period is used in the controller)

ExactlyClockedWithDiscreteController

Modelica_Synchronous.Examples.SimpleControlledDrive

Simple controlled drive with discrete controller and exact periodic clocks (period is used in the controller)

ClockedWith_AD_DA_Effects

Modelica_Synchronous.Examples.SimpleControlledDrive

Simple controlled drive with discrete controller and simulated AD and DA effects

SubClocked

Modelica_Synchronous.Examples.CascadeControlledDrive

Drive with clocked cascade controller where clocks are defined with sub-sampling and partitions with super-sampling

SuperSampled

Modelica_Synchronous.Examples.CascadeControlledDrive

Drive with clocked cascade controller where fastest partition is defined with a clock and slower partition is defined with super-sampling

AbsoluteClocks

Modelica_Synchronous.Examples.CascadeControlledDrive

Drive with clocked cascade controller where all partitions are defined with exact (integer) clock that need to be compatible to each other

TestReplaceableSamplerHold

Modelica_Synchronous.WorkInProgress.Tests

Using partial sample and hold blocks to allow redeclaration of blocks to simulated communication blocks