WOLFRAM SYSTEM MODELER
PIDiscrete-time PI controller with clocked input and output signals (for periodic and aperiodic systems using the parameterization of the continuous PI controller) |
SystemModel["Modelica_Synchronous.RealSignals.NonPeriodic.PI"]
Discrete-time PI controller that has been derived from the continuous-time PI controller
1 y = k * (1 + ---) * u T*s T*s + 1 = k * ------- * u T*s
by using the implicit Euler discretization formula. The block is parametrized with the gain k and the time constant T of the continuous PI block. As a result, the discrete-time form of the PI controller depends explicitly on the sample time of the controller and changing this sample time, will give still a similar performance.
k |
Value: Type: Real Description: Gain of continuous PI controller |
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T |
Value: Type: Real Description: Time constant of continuous PI controller |
x |
Type: Real Description: Discrete PI state |
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u |
Type: RealInput Description: Connector of clocked, Real input signal |
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y |
Type: RealOutput Description: Connector of clocked, Real output signal |
Modelica_Synchronous.Examples.SimpleControlledDrive Simple controlled drive with discrete controller (period is used in the controller) |
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ExactlyClockedWithDiscreteController Modelica_Synchronous.Examples.SimpleControlledDrive Simple controlled drive with discrete controller and exact periodic clocks (period is used in the controller) |
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Modelica_Synchronous.Examples.SimpleControlledDrive Simple controlled drive with discrete controller and simulated AD and DA effects |
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Modelica_Synchronous.Examples.CascadeControlledDrive Drive with clocked cascade controller where clocks are defined with sub-sampling and partitions with super-sampling |
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Modelica_Synchronous.Examples.CascadeControlledDrive Drive with clocked cascade controller where fastest partition is defined with a clock and slower partition is defined with super-sampling |
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Modelica_Synchronous.Examples.CascadeControlledDrive Drive with clocked cascade controller where all partitions are defined with exact (integer) clock that need to be compatible to each other |
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Modelica_Synchronous.WorkInProgress.Tests Using partial sample and hold blocks to allow redeclaration of blocks to simulated communication blocks |